There is a rapidly growing trend for mobile and remote data access over high-speed communication networks, such as 3G or 4G cellular networks. However, accurately delivering and deciphering data streams over these networks has become increasingly challenging and difficult. High-speed communication networks which are capable of delivering information include, but are not limited to, wireless networks, cellular networks, wireless personal area networks (“WPAN”), wireless local area networks (“WLAN”), wireless metropolitan area networks (“MAN”), or the like. While WPAN can be Bluetooth or ZigBee, WLAN may be a Wi-Fi network in accordance with IEEE 802.11 WLAN standards.
To communicate high speed data over a communication network, such as a long-term evolution (LTE) communication network, the network needs to support many configurations and process data utilizing different FFT sizes. A variety of architectures have been proposed for pipelined FFT processing that are capable of processing an uninterrupted stream of input data samples while producing a stream of output data samples at a matching rate. However, these architectures typically utilize multiple stages of FFT radix processors organized in a pipelined mode. The data is streamed into a first stage to complete a first radix operation and then the data is stream to subsequent stages for subsequent radix operations.
Thus, conventional pipelined architectures utilize multiple physical radix processors laid out in series to create the pipeline for streaming in/out data. The number of stages utilized is determined by the largest FFT size to be supported. However, this design becomes more complex when processing a variety of FFT sizes that require mixed-radix (2, 3, 4, 5, and 6) processing typically used in cellular (e.g., LTE) transceivers. As a result, the drawbacks of conventional systems are not only the amount of hardware resources utilized, but also the difficulty to configure such a system with the many different FFT sizes and mixed-radix factorization schemes utilized in an LTE transceiver.
Therefore, it is desirable to have a pipelined FFT architecture that is faster and consumes fewer resources than conventional systems. The architecture should have a higher performance to power/area ratio than the conventional architectures, and achieve much higher scalability and programmability for all possible mix-radix operations.